APPLICATION

Open vSwitch accelerator

Open vSwitch accelerator

We develop Open vSwitch accelerator in Intel Arria10 development kit.
Axonerve can improbe speed at 10 times in data search.

Configuration
FPGA Axonerve Configuration Application
Vendor Series CAM
type
Memory mode Key
length
[bit]
Entry
depth
Core
clock
[MHz]
Intel Arria 10 TCAM on chip memory 288 16K 100MHz Open vSwith accelerator

Overall demo system

Overall demo system

Axonerve accelerator card image

Axonerve accelerator card image

Accelerator demonstration result

Accelerator demonstration result

Xilinx SDNet design

Xilinx SDNet-based 100G wire speed packet filtering system

We develop 100G packet filtering system in the Virtex UltraScale FPGA VCU110 development kit.
This system is optimal platform for developing systems that require big data processing.

Configuration
FPGA Axonerve Configuration Application
Vendor Series CAM
type
Memory mode Key
length
[bit]
Entry
depth
Core
clock
[MHz]
Xilinx Virtex UltraScale TCAM on chip memory 296 32K 170 SDNet reference design

Demo on VCU110 Development Kit (1)

Demo on VCU110 Development Kit (1)

Xilinx UltraScale

Entry Table

Test Pattern

Demo on VCU110 Development Kit (2)

Demo on VCU110 Development Kit (2)

Packet filtering evaluation kit

Packet filtering evaluation kit

Packet filtering evaluation kit is e-trees Japan company's e7UDP/IP and e7PCIe evaluation platform.
It is easy that you can develop application used CAM in FPGA.

Configuration
FPGA Axonerve Configuration Application
Vendor Series CAM
type
Memory mode Key
length
[bit]
Entry
depth
Core
clock
[MHz]
Xilinx Kintex7 TCAM on chip memory 288 4K 150 Reference design for
packet filtering system
Intel Stratix V TCAM on chip memory 288 4K 150 Reference design for
packet filtering system

Packet filtering evaluation kit

Packet filtering evaluation kit

Text Search

Text Search

We develop Text search system in Stratix V FPGA board.
Axonerve, UDP I/F and control logic are implemented in the FPGA.

Configuration
FPGA Axonerve Configuration Application
Vendor Series CAM
type
Memory mode Key
length
[bit]
Entry
depth
Core
clock
[MHz]
Intel FPGA (Altera) Stratix V TCAM on chip memory 288 4K 150 IP evaluation system

Text Search

Axonerve text search demo environment.

Accelerator for network system

Accelerator for network system

We develop accelerator for network system in Stratix V FPGA board.
Axonerve provides two types of mask field.

Configuration
FPGA Axonerve Configuration Application
Vendor Series CAM
type
Memory mode Key
length
[bit]
Entry
depth
Core
clock
[MHz]
Intel FPGA (Altera) Stratix V TCAM on chip memory 288 4K 150 IP evaluation system

Accelerator for network system

Search Acceleration System Example

Search Acceleration System Example

Axonerve provides two types of bit-field assignment presetting of key data.
Type1 application demonstration movie.

Type2 application demonstration movie.